Media Summary: This is a screen recording of a software-defined central processing unit running in a simulator. Derived from work at ... Ever wondered what actually exists inside the Programmable Logic (PL) of a Zynq SoC? This hands-on FPGA architecture video ... Reverse engineering old custom chips from ...

The Zipcpu A Resource Efficient - Detailed Analysis & Overview

This is a screen recording of a software-defined central processing unit running in a simulator. Derived from work at ... Ever wondered what actually exists inside the Programmable Logic (PL) of a Zynq SoC? This hands-on FPGA architecture video ... Reverse engineering old custom chips from ... IBM Z teams are under increasing pressure to control costs, protect production windows, and keep pace with growing data ... Have you ever wondered what's inside an FPGA? In this video, I'm going to take you on a journey inside FPGAs, peeling back the ... I transformed the inner loop - implementation time fell from days to hours. The outer loop didn't move. CI is the new bottleneck, ...

High-performance computing and data-intensive infrastructures are increasingly limited by data movement rather than processing ...

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The ZipCPU: A resource efficient 32-bit SoftCore - ORCONF 2016
Lessons learned while formally verifying the ZipCPU - Dan Gisselquist - ORConf 2018
ZipCPU Simulator in Action
Inside the Zynq FPGA (Hands-On) | SLICEL, SLICEM, DSP48 & BRAM Explained
giulioz: MMO-CHIP: From Microscope to Verilog in an hour
Optimizing IBM Z Operations: Reducing Cost and Risk Through Smarter Sort and Storage Management
What's Inside an FPGA? | Exploring the Hardware Resources in FPGAs
The outer loop is the bottleneck: Shipping at the speed of AI - Eli Schleifer | PlatformCon 2026
Accelerating Data: Lossless Compression in FPGA(Calliope-Louisa Sotiropoulou)
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The ZipCPU: A resource efficient 32-bit SoftCore - ORCONF 2016

The ZipCPU: A resource efficient 32-bit SoftCore - ORCONF 2016

... we'll talk about three ways that

Lessons learned while formally verifying the ZipCPU - Dan Gisselquist - ORConf 2018

Lessons learned while formally verifying the ZipCPU - Dan Gisselquist - ORConf 2018

The ZipCPU

ZipCPU Simulator in Action

ZipCPU Simulator in Action

This is a screen recording of a software-defined central processing unit running in a simulator. Derived from work at ...

Inside the Zynq FPGA (Hands-On) | SLICEL, SLICEM, DSP48 & BRAM Explained

Inside the Zynq FPGA (Hands-On) | SLICEL, SLICEM, DSP48 & BRAM Explained

Ever wondered what actually exists inside the Programmable Logic (PL) of a Zynq SoC? This hands-on FPGA architecture video ...

giulioz: MMO-CHIP: From Microscope to Verilog in an hour

giulioz: MMO-CHIP: From Microscope to Verilog in an hour

https://media.ccc.de/v/gpn24-616-mmo-chip-from-microscope-to-verilog-in-an-hour Reverse engineering old custom chips from ...

Optimizing IBM Z Operations: Reducing Cost and Risk Through Smarter Sort and Storage Management

Optimizing IBM Z Operations: Reducing Cost and Risk Through Smarter Sort and Storage Management

IBM Z teams are under increasing pressure to control costs, protect production windows, and keep pace with growing data ...

What's Inside an FPGA? | Exploring the Hardware Resources in FPGAs

What's Inside an FPGA? | Exploring the Hardware Resources in FPGAs

Have you ever wondered what's inside an FPGA? In this video, I'm going to take you on a journey inside FPGAs, peeling back the ...

The outer loop is the bottleneck: Shipping at the speed of AI - Eli Schleifer | PlatformCon 2026

The outer loop is the bottleneck: Shipping at the speed of AI - Eli Schleifer | PlatformCon 2026

I transformed the inner loop - implementation time fell from days to hours. The outer loop didn't move. CI is the new bottleneck, ...

Accelerating Data: Lossless Compression in FPGA(Calliope-Louisa Sotiropoulou)

Accelerating Data: Lossless Compression in FPGA(Calliope-Louisa Sotiropoulou)

High-performance computing and data-intensive infrastructures are increasingly limited by data movement rather than processing ...