Media Summary: In this video cover basic concepts of fixed size array. 00:00 Intro 00:09 reg / wire 00:34 reg / wire rule 00:49 Synthesis perspective 01:21 Simulation perspective 00:00 Introduction 00:18 Transistor as a switch 01:10 Building logic gates from transistors
Systemverilog Tutorial 02 What Is - Detailed Analysis & Overview
In this video cover basic concepts of fixed size array. 00:00 Intro 00:09 reg / wire 00:34 reg / wire rule 00:49 Synthesis perspective 01:21 Simulation perspective 00:00 Introduction 00:18 Transistor as a switch 01:10 Building logic gates from transistors 00:00 Introduction 00:29 Creating new type 01:42 Simple class example 00:08 Using only blocking assignments with module instances 00:31 Using program as a test "module" 00:55 Visualizing real ...
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