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FPGA Video Processing HDL Kernel #1

FPGA Video Processing HDL Kernel #1

VHDL

FPGA Video Processing HDL Kernel #4

FPGA Video Processing HDL Kernel #4

VHDL

FPGA Video Processing HDL Kernel #0

FPGA Video Processing HDL Kernel #0

Design a variable

FPGA Video Processing HDL Kernel #3

FPGA Video Processing HDL Kernel #3

Scalable adder tree for

FPGA Video Processing HDL Kernel # 5

FPGA Video Processing HDL Kernel # 5

VHDL

FPGA Video Processing HDL Kernel #2

FPGA Video Processing HDL Kernel #2

Scalable

FPGA Video Processing 5x5 Kernel

FPGA Video Processing 5x5 Kernel

HLS Image

PSX on FPGA (Kernel run)

PSX on FPGA (Kernel run)

R3000A, GPU status, OTC DMA Implemented. BIOS and

FPGA video processing Demo

FPGA video processing Demo

FPGA video processing Demo

Open Source HDL Co Simulation with AMD Alveo (Matthias Kern)

Open Source HDL Co Simulation with AMD Alveo (Matthias Kern)

HDL

FPGA Video Processing Line Buffers #0

FPGA Video Processing Line Buffers #0

VHDL

What's an FPGA?

What's an FPGA?

In the

Machine Learning on FPGAs: Circuit Architecture and FPGA Implementation

Machine Learning on FPGAs: Circuit Architecture and FPGA Implementation

Lecture 3 of the project to implement a small neural network on an