Media Summary: Cadence Xcelium Logic Simulator is redefining performance for multi-core machines and multi-die systems. In this video, Alok ... Artifact: Paper's code can be found at: The gem5 profiling tool we used: ... Link to Download PPT Discussed in this Video :

Distributed Simulation For Chiplets 3 - Detailed Analysis & Overview

Cadence Xcelium Logic Simulator is redefining performance for multi-core machines and multi-die systems. In this video, Alok ... Artifact: Paper's code can be found at: The gem5 profiling tool we used: ... Link to Download PPT Discussed in this Video : For decades, Moore's Law powered the exponential growth of computing. But as transistor scaling hits physical and economic ... Presented by Jawad Nasrullah (Palo Alto Electron) Tony Mastroianni (Siemens) The design of In this episode of The GeekNarrator podcast, host Kaivalya Apte dives into the complexities of testing

Everyone measures an AI chip by its compute. But a modern accelerator spends most of its energy and area not on math, but on ... One die to control everything – this has been the paradigm of processor manufacturers for a long time. But everything is changing, ...

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Distributed Simulation for Chiplets (3× Faster with Xcelium)
Fast-Forward Verification: Scaling Chiplet Simulations with Xcelium
How to Simulate Chiplets 3x Faster with Xcelium
Xcelium Distributed Simulation App Accelerates Multi-Die Simulations Up to 3X
"Testing Distributed Systems w/ Deterministic Simulation" by Will Wilson
[ISCA 2026] DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
Chiplets Explained |The Future of Semiconductor Industry | UCIe 3.0 Protocol Overview|Future of VLSI
CHIPLETS = FUTURE ?
Using CDXML/JEP30 Models for Chiplet Design and Verification
Testing Distributed Systems the right way ft. Will Wilson
Cost Modeling Analysis for Heterogeneous Integration of Chiplets
SerDes: The Real Bottleneck in AI Chips (PAM4, Chiplets, Optics)
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Distributed Simulation for Chiplets (3× Faster with Xcelium)

Distributed Simulation for Chiplets (3× Faster with Xcelium)

Chiplet

Fast-Forward Verification: Scaling Chiplet Simulations with Xcelium

Fast-Forward Verification: Scaling Chiplet Simulations with Xcelium

Chiplet

How to Simulate Chiplets 3x Faster with Xcelium

How to Simulate Chiplets 3x Faster with Xcelium

Chiplet

Xcelium Distributed Simulation App Accelerates Multi-Die Simulations Up to 3X

Xcelium Distributed Simulation App Accelerates Multi-Die Simulations Up to 3X

Cadence Xcelium Logic Simulator is redefining performance for multi-core machines and multi-die systems. In this video, Alok ...

"Testing Distributed Systems w/ Deterministic Simulation" by Will Wilson

"Testing Distributed Systems w/ Deterministic Simulation" by Will Wilson

Debugging highly concurrent

[ISCA 2026] DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

[ISCA 2026] DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

Artifact: Paper's code can be found at: https://zenodo.org/records/19428665 The gem5 profiling tool we used: ...

Chiplets Explained |The Future of Semiconductor Industry | UCIe 3.0 Protocol Overview|Future of VLSI

Chiplets Explained |The Future of Semiconductor Industry | UCIe 3.0 Protocol Overview|Future of VLSI

Link to Download PPT Discussed in this Video : https://topmate.io/nc_chandu/2160782 ...

CHIPLETS = FUTURE ?

CHIPLETS = FUTURE ?

For decades, Moore's Law powered the exponential growth of computing. But as transistor scaling hits physical and economic ...

Using CDXML/JEP30 Models for Chiplet Design and Verification

Using CDXML/JEP30 Models for Chiplet Design and Verification

Presented by Jawad Nasrullah (Palo Alto Electron) | Tony Mastroianni (Siemens) The design of

Testing Distributed Systems the right way ft. Will Wilson

Testing Distributed Systems the right way ft. Will Wilson

In this episode of The GeekNarrator podcast, host Kaivalya Apte dives into the complexities of testing

Cost Modeling Analysis for Heterogeneous Integration of Chiplets

Cost Modeling Analysis for Heterogeneous Integration of Chiplets

Key to the decision making on

SerDes: The Real Bottleneck in AI Chips (PAM4, Chiplets, Optics)

SerDes: The Real Bottleneck in AI Chips (PAM4, Chiplets, Optics)

Everyone measures an AI chip by its compute. But a modern accelerator spends most of its energy and area not on math, but on ...

CHIPLETS: Divide and Conquer | The Future of Processors

CHIPLETS: Divide and Conquer | The Future of Processors

One die to control everything – this has been the paradigm of processor manufacturers for a long time. But everything is changing, ...